The present invention relates to a manufacturing method of a semiconductor device, particularly to a technology that is effective when applied to the manufacturing of a semiconductor element having a metal silicide layer.
As higher integration of a semiconductor device advances, a field effect transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) is more miniaturized according to the scaling law. On that occasion however, an arising problem is that resistance in a gate electrode and a source/drain region increases and high speed operations cannot be obtained even though a field effect transistor is miniaturized. To cope with the problem, a salicide (Self Aligned Silicide) technology, which reduces resistance in a gate electrode and a source/drain region by forming a low resistance metal silicide layer such as a nickel silicide layer or a cobalt silicide layer over the surfaces of a conductive film configuring the gate electrode and a semiconductor region configuring the source/drain region through self-aligning, is studied.
Japanese Unexamined Patent Publication No. 2004-521486 describes a technology that makes the thickness of a silicide formed at the edge of a silicon electrode substantially equal with the thickness of the center part of the electrode by a two-step annealing method. More specifically, the patent publication: describes a technology of forming Ni2Si and Ni3Si in a silicide layer through a first heat treatment (250° C. to 350° C.) with an annealing apparatus using laser annealing, lamp heating, or radiation annealing and forming nickel monosilicide in the silicide layer through a second heat treatment (350° C. to 700° C.); but does not describe that microcrystals of NiSi are formed in the silicide layer through the first heat treatment. Further, the patent publication describes that an Ni alloy film is formed as a metal film formed over a semiconductor substrate before the first heat treatment, but neither exemplifies any specific alloy film such as an Ni—Pt film nor describes that a thermal conductive annealing apparatus is used at heat treatment for forming a silicide layer.
Japanese Unexamined Patent Publication No. 2007-299899 describes a technology of forming a silicide layer including nickel monosilicide by: inhibiting surface oxidization of the silicide layer; and not increasing sheet resistance in the silicide layer. More specifically, the patent publication: describes a technology of, after forming an Ni film and a TiN film in sequence over a semiconductor substrate, forming Ni2Si in a silicide layer through a first temperature treatment (200° C. to 350° C.) by a sinter heating method and forming nickel monosilicide in the silicide layer through a second temperature treatment (370° C. to 500° C.) by the same sinter heating method; but does not describe that the microcrystals of NiSi are formed in the silicide layer through the first temperature treatment. Further, the patent publication: describes that an Ni film is used as a metal film formed over a semiconductor substrate before the first temperature treatment; but does not describe that an Ni alloy film such as an Ni—Pt film is formed.
Japanese Unexamined Patent Publication No. 2009-176975 describes a technology of forming a nickel platinum silicide layer through a salicide process of a whole reaction type.